1. Field of the Invention
The present invention relates to a structure of an input protecting device provided in a signal input portion of a semiconductor circuit device.
2. Description of the Prior Art
FIG. 1 is a view showing a structure of a complementary MOS integrated circuit with a conventional input protecting circuit. Referring to FIG. 1, is shown an input portion of a system S2 which comprises, for example, a printer and the like operating in response to an output from a system S1 which comprises, for example, a micro computer and the like. The system S1 comprises in an output portion thereof an output buffer formed of an inverter having a P-channel MOS transistor T1 and an N-channel MOS transistor T2 connected in a complementary manner. An output signal from the system S1 is applied to an input terminal 1 of the system S2 through the output buffer. The system S2 comprises in the input portion a first clamping diode 3 connected between the input terminal 1 and a first power supply terminal 8 for clamping a voltage applied to the input terminal 1 to a predetermined voltage in case that the applied voltage is larger than a first predetermined voltage value, a second clamping diode 4 connected between the signal input terminal 1 and a second power supply terminal 9 for clampling the voltage applied to the signal input terminal 1 to a predetermined voltage in case that the applied voltage is smaller than a second predetermined voltage value, an input protective resistor 5 connected to a connecting point of the clamping diodes 3 and 4, and an inverter (input buffer) comprising a P-channel MOS transistor 6 and an N-channel MOS transistor 7 for outputting, after inversion, a signal received through the input protective resistor 5. An inverter output is applied to an internal circuit (not shown) through an internal output terminal 2, so that the internal circuit operates in response to a signal provided. The system S1 generates an internal supply potential V.sub.CC in response to a supply potential from an external power supply V.sub.A. The potential V.sub.CC is used as an operation supply potential for the system S1. The system S2 receives a supply potential from an external power supply V.sub.B on the power supply terminal 8 and then generates the internal supply potential V.sub.CC which is used as an operation supply potential. Assuming that the potential V.sub.CC applied to the first power supply terminal 8 is positive potential and a potential second power supply terminal 9 is a ground potential in the system S2, an operation is now described. The system S2 operates in response to an output signal of the system S1. In this case, let it be assumed that an operation supply potential is supplied to respective systems S1 and S2 via the respective external power supplies V.sub.A and V.sub.B. At this time, the input clamping diode 3 functions to clamp an input voltage to a level of "(supply potential V.sub.CC +V.sub.F)" when an overvoltage higher than the supply potential V.sub.CC is applied to the input terminal 1 of the system S2. The V.sub.F shows a forward voltage drop of the input clamping diode 3. On the other hand, the input clamping diode 4 functions to clamp an input voltage to a level of "(ground potential-V.sub.F)" when a voltage lower than a ground potential is applied to the input terminal 1. This prevents the overvoltage from being supplied to the inverter stage and the internal circuit.
The above-mentioned description was made, assuming that forward voltage drops of both input clamping diodes 3 and 4 are equally V.sub.F.
A conventional input protecting circuit in the system S2 performs the above-mentioned operation. Therefore, an input protecting function can be achieved when an operation supply potential is supplied to both systems S1 and S2. However, for example, if the system S1 is a personal computer and the system S2 is a printer serving as an external apparatus, it could happen that the power supply V.sub.A is supplied to the system S1 while the operation supply potential is not supplied from the external power supply V.sub.B to the system S2. In this case, that is, when the operation supply potential V.sub.CC is not applied to the power supply terminal 8 of the system S2, a case could happen in which a signal of "H" level is applied from the system S1 to the signal input terminal 1. In this case, a current continues to flow from the input terminal 1 to the power supply terminal 8 through the input clamping diode 3, since the power supply terminal 8 is at "L" level. Therefore, in this state, it becomes a large load for a power supply (i.e., a power supply for supplying the operation supply potential of the system S1) supplying a signal of "H" level to the input terminal 1. In addition, there were problems in which the potential of the power supply terminal 8 rises and the internal circuit of the system S2 erroneously operates due to the raised potential, when an input impedance of a power supply providing the operation supply potential to the power supply terminal 8 is high. Therefore, there were problems in which a semiconductor circuit device with an input protecting circuit structured by using the conventional input clamping diodes can not be used in an interface portion of a system.
Furthermore, in order to avoid the above-mentioned malfunction, a method of structuring an I/O portion using bipolar transistors can be considered, but in this case, problems are caused in which a consumed power becomes large.
A structure of an input protecting circuit with the above-mentioned input clamping diodes is shown, for example, in page 469 of RCA Solid State Q MOS Data Book.